The present invention relates to a combiner for combining digital data samples from a predetermined number of inputs to a predetermined number of outputs, for example from a predetermined number of channels, onto a predetermined number of carriers of a digital communication system.
In telecommunication systems, a large number of channels, e.g. user channels containing voice or data signals, may be transmitted together via the same transmission medium, for example, via the same radio frequency band. A multitude of access schemes for placing the data of the user channels on the transmission medium is known. One class of transmission schemes simultaneously transmits a plurality of different user channels, e.g. in a radio frequency band, in such a way that they overlap in the time domain as well as in the frequency domain. A well-known access scheme of this class is the CDMA (Code Division Multiple Access) scheme.
Although the invention is not limited to the CDMA scheme and may be used in any digital communication system where a number of digital data samples from a predetermined number of inputs (e.g. user channels or some sort of preadded channels) must be combined flexibly onto a predetermined number of outputs, (e.g. carriers), the invention in particular relates to a flexible CDMA combiner, where the digital data samples are represented by weighted chips generated in a base station of a CDMA radio communication system.
FIG. 1 shows a typical block diagram of a conventional baseband CDMA transmitter in a CDMA base transceiver station BTS. Data on a plurality of user channels ch-1, ch-2, . . . ch-n are input to a channel encoder 1. Apart from channel coding itself, the channel encoder 1 may perform a QPSK modulation, time-alignment of the user data etc. The channel encoder 1 outputs a possibly complex-valued output data symbol stream (ODSS) which is input to a spreader/power weighting unit 2 which receives spreading codes and power weights for the individual channels. Each user channel is spread with a specific spreading code and after spreading each channel is power weighted before all channels xcfx861, xcfx862, . . . xcfx86n are output to a combiner 3 where they are combined. Note that xcfx861, xcfx862, . . . xcfx86n may refer to the real and imaginary parts of complex-value channels. The output of the spreader/power weighting unit 2 are sets of weighted chips which are output at a chip rate CLK. That is, within each period t0-t1, t1-t2, . . . tkxe2x88x921-tk a single weighted chip of each channel is output parallely. Each weighted chip contains a predetermined number of bits, i.e. each digital data sample has a predetermined bit width (hereinafter denoted as in bit) due to power weighting.
In a CDMA communication system a (geographical) area is divided into several regions which are called sectors. In each sector, at least one and possibly more carriers are used where each carrier represents a particular frequency band. Within each sector the carrier can have a different number of channels. In the following description, the term xe2x80x9csector-carrierxe2x80x9d represents basically a combination of a particular sector with a particular carrier (frequency band). The task of the combiner 3 is to combine the data of all the channels, which must be transmitted in a specific sector and on a specific carrier. Thus, the combiner 3 is essentially an adder which adds up the discrete instantaneous values of all channels belonging to a given sector-carrier. As is indicated in FIG. 1 there may be m sector-carriers sc-1, sc-2, . . . sc-m.
Typically, in a CDMA transmitter, the number of channels to be added for each such sector-carrier is fixed by the hardware implementation. Since a separate (but identical) combiner hardware is used for each sector-carrier, this results in an equal number of channels on each sector-carrier of a base transceiver station BTS. On the other hand, in contradiction to this fixed equal number of channels, the network operator of a CDMA system faces in practice a different load in each of the sector-carriers. Therefore, the network operator would like to configure a variable number of user channels for each sector-carrier. For example, a base transceiver station BTS on a highway requires a higher number of user channels in the sectors covering this highway, whereas other sectors (for example covering a rural or mountainous area) may only have to handle a few user channels. Furthermore, the load in the individual sectors might also change over time, e.g. during rush-hours, holiday seasons or trade fairs.
Thus, having a fixed number of channels per sector-carrier implies that the network operator has always to provide a high number of user channels for all sector-carriers no matter whether or not they are actually required in a particular point in time.
Thus, it is desirable to provide the network operator with a flexible combiner, which allows the network operator to tailor the number of available channels per sector-carrier according to the load conditions in the system. With the flexible combiner the network operator could buy a standard base transceiver station BTS having the capability to process a certain total number of channels, and could adapt the base transceiver station BTS to the actual distribution of channels over the sectors and carriers without wasting ressources. The flexible combiner could return benefits also to the supplier with less cost for adapting his equipment to the customer""s needs.
Prior Art Solutions
When the number of channels to be combined onto a specific sector-carrier is fixed and does not change over time a combiner as shown in FIG. 2-1 and denoted with reference numeral 3-1 can be used. In this combiner 3-1 the channels xcfx861, xcfx862, xcfx863, xcfx864 are invariably combined onto the sector-carrier sc-1 and the channels xcfx86n-3, xcfx86n-2, xcfx86n-1, xcfx86n are combined onto the sector-carrier sc-m. The channels are respectively added in pairs in the adders ADD1, and stored in intermediate flip-flops FF1 whereafter the respective outputs are added by an adder ADD2 and the output of the adder ADD2 is stored in a further intermediate flip-flop FF2. This type of circuit must be provided for each of the m sector-carriers. For the example in FIG. 2-1, where 4 channels per sector-carrier are combined, n (total number of channels) is equal to m*4 (m: number of sector-carriers). The combiner 3-1 in FIG. 2-1 has the disadvantage that the channels are invariably combined onto the sector-carriers and furthermore, the combiner 3-1 needs quite an extensive hardware, since the respective circuits need to be provided m-times.
FIG. 2-2 shows a combiner 3-2 which allows to reduce the hardware complexity. Such a combiner is described in EP 98 121 518.9 filed by the same applicant as the present application. Essentially, the combiner 3-2 in FIG. 2-2 comprises m adders ADD5, m flip-flops FF5 and m flip-flops FF6. The outputs of the flip-flops FF5 are respectively coupled to the input of the adder ADD5 which also receives the output of a respective multiplexer MUX which is also provided m-times. If in FIG. 2-2, similarly as in FIG. 2-1, again 4 channels (such as xcfx862, xcfx863, xcfx864 or xcfx86n-3, xcfx86n-2, xcfx86n-1, xcfx86n) are to be combined onto each sector-carrier, then the respective adder ADD5 and the respective multiplexer MUX have to be operated at four times the chip rate CLK in order to add one weighted chip of each of the respective four channels in a single chip period 1/CLK. The limiting factor in FIG. 2-2 is thus the maximum operating frequency of the adder.
The combiner 3-2 of FIG. 2-2 provides more flexibility than the combiner 3-1, since for combining e.g. 8 instead of 4 channels per sector-carrier, the adder ADD5 could operate at twice the rate (i.e. 8*CLK) and the MUX could be provided with 8 instead of 4 inputs while in the combiner 3-1 a further hierarchical adder-stage would be necessary. However, the flexibility problem, i.e. that e.g. xcfx861 can only be used for the output sc-1, remains the same.
FIG. 2-3 shows a combiner 3-3 which increases the flexibility. The circuit in FIG. 2-3 is a modification of the circuit shown in FIG. 2-1. In FIG. 2-3 the combiner 3-3 comprises a number of multiplexers MUX at each input of the respective adder ADD3. For each sector-carrier, for example the sector-carrier sc-1, the adder ADD3 and the flip-flop FF3 are provided n/2-times and the multiplexer MUX is provided n-times. A control signal sel is applied to the individual multiplexers MUX in order to allow the adding of predetermined ones of the n-channels onto a single sector-carrier. If certain channels are not configured for one sector-carrier, they are set to 0 by the signal sel applied to the multiplexer. Whilst the circuit in FIG. 2-3 is far more flexible than the one in FIG. 2-2, since the combiner 3-3 allows to combine any input user channel onto any desired sector-carrier, there is an extensive hardware necessary in order to realize the circuit.
As explained above, the disadvantage of the combiner 3-1 in FIG. 2-1 is that it provides the same maximum number of e.g. 4 channels to a respective sector-carrier. Furthermore, each channel is invariably attributed to a specific sector-carrier. Therefore, it is for example not possible to feed any of the channels xcfx86n-3 . . . xcfx86n to a sector-carrier other than sc-m. Thus, the circuit in FIG. 2-1 offers no flexibility and the hardware is inefficiently used. The combiner 3-2 in FIG. 2-2 uses the hardware more efficiently due to the provision of the multiplexer MUX, but it still has no flexibility because it still provides the same number of e.g. 4 channels to a predetermined sector-carrier and does not allow to feed the channels to an arbitrarily selected sector-carrier. Whilst the combiner 3-3 maximizes the flexibility and allows to combine any channel onto any desired sector-carrier, the hardware is very extensive to realize such a circuit. That is, hardware is wasted, because some of the adders may not be needed in particular ones of the sectors. If one considers that a typical number for n in a CDMA radio communication system is n=24 (furthermore, in a practical implementation, each of 24 input channels to the combiner could be constituted by 32 preadded channels, i.e. xcfx861=ch1+ch2+ . . . ch32; xcfx862=ch33+ch34+ . . . ch64 etc., where xe2x80x9cchxe2x80x9d denotes a particular user channel), there is an extremely high hardware effort necessary to realize the flexibility in channel combining when using the circuit 3-3 in FIG. 2-3.
The object of the present invention is to provide a combiner which can combine in a flexible way a predetermined number of user channels onto a predetermined number of carriers without using complicated hardware.
Solution of the Object
This object is solved (claim 1) according to the invention by a combiner for combining digital data samples from a predetermined number n of inputs onto a predetermined number m of outputs, said digital data samples having a predetermined bit width and arriving parallely at said combiner as data sets respectively consisting of one data sample from each input at a predetermined common sample rate CLK, including a plurality of k subprocessing units SU1,SU2, . . . ,SUixe2x88x921, SUi, . . . ,SUk which each comprises an input register for downsampling and storing arriving data sets at a clock rate of CLK/k, and a multiplex/add means for receiving said data sets stored in said input register and for outputting at said clock rate of CLK/k, for each of said m outputs, an added data sample respectively formed by an addition of predetermined ones of said stored data samples; and a selector for cyclically selecting at said common data rate CLK from said multiplex/add means of said subprocessing units a respective output data set consisting of said m added data samples, and wherein the sampling phase of the input register of subprocessing unit SUi is delayed by 1/CLK with respect to the sampling phase of the input register of the subprocessing unit SUixe2x88x921 with i in the range of 2, . . . ,K.
This object is also solved (claim 9) by a combiner for combining digital data samples from a predetermined number n of inputs onto a predetermined number m of outputs said digital data samples having a predetermined bit width (in_bit) and arriving parallely at said combiner as data sets respectively consisting of one data sample from each input at a predetermined common data rate CLK, comprising a plurality of k subprocessing units SU1, SU2, . . . ,SUixe2x88x921, SUi, . . . ,SUk which respectively include an input register for downsampling and storing arriving data sets at a clock rate of CLK/k; and a multiplex/add means for receiving said data sets stored in said input register and for outputting at said clock rate of CLK/k, for each of said m outputs, an added data sample respectively formed by an addition of predetermined ones of said stored data samples, and a selector for cyclically selecting at the common data rate CLK from said multiplex/add means of said subprocessing units a respective output data set consisting of said m added data samples; and wherein the sampling phase of the input register of subprocessing unit SUi is delayed by 1/CLK with respect to the sampling phase of the input register of the subprocessing unit SUixe2x88x921, where i=2,3, . . . ,k, wherein an input means is provided for inputting the data sets to each of said input registers of said k subprocessing units at the common data rate CLK, wherein each of multiplex/add means comprises a multiplexer for sequentially selecting, for each of said m outputs, said predetermined ones of said stored data samples, at a clock rate of OS*CLK, where OS=n/k is an oversampling factor; an adder for adding for each of said m outputs said selected data samples into said respective added data sample at said clock rate OS*CLK; and an output register for storing for said m outputs an output data set comprising said m added data samples, wherein said selector selects said output data sets from said respective output register of said subprocessing units; and an output means is provided for outputting said selected output data sets on said outputs at said common data rate CLK, wherein each adder comprises a first adder register taking in said samples selected by said multiplexer at said clock rate of OS*CLK and an addition unit receiving as inputs an output from said first adder register and an output from an adder multiplexer and outputting added samples of said inputs to a second adder register taking in said added samples at said clock rate of OS*CLK, said adder multiplexer receiving as inputs an output from said second adder register and a digital xe2x80x9c0xe2x80x9d signal.
Such combiners provide for two kinds of flexibility, namely each input channel can reach each output and the number of input channels to be combined onto an output can be variable from output to output. The principle idea of the invention is to provide a plurality of subprocessing units each of which is provided with a respective set of data samples at each k-th chip period, i.e. at a rate of CLK/k. In the subprocessing units the selection and adding is carried out at an oversampling rate which is higher than the chip rate. The output of each subprocessing unit is an intermediate downsampled result for the outputs (sector-carriers) 1 to m. The selector reads out these intermediate results and interleaves them to form a result at the chip rate CLK.
Therefore, instead of providing a large number of multiplexers as in FIG. 2-3, the basic concept of the invention is to provide subprocessing units k-times whilst increasing the processing rate in the subprocessing units. Therefore, the flexibility is maintained and the hardware complexity is minimized. Thus, the hardware costs can be reduced.
Each adder in the subprocessing unit can preferrably comprise a first adder register taking in said samples selected by said multiplexer at said clock rate of OS*CLK and an addition unit receiving as inputs an output from said first adder register and an output from an adder multiplexer and outputting added samples of said inputs to a second adder register taking in said added samples at said clock rate of OS*CLK, said adder multiplexer receiving as inputs an output from said second adder register and a digital xe2x80x9c0xe2x80x9d signal, similarly as the adder shown in FIG. 2-2.
Further advantageous embodiments of the invention are listed in the dependent claims. Hereinafter, the invention would be described with reference to its advantageous embodiments. However, it should be noted that the teaching as disclosed in the description is not limited to the specially preferred embodiment which is currently considered to be the best mode of the invention. That is, on the basis of the description, the drawings and the claims various modifications and variations of the invention are possible. In particular, the invention can comprise embodiments which result from a combination of features which have been separately described in the specification and/or listed in the appended claims.